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SANTA CLARA, Calif. , May 12 /PRNewswire-FirstCall/ -- A new serializer and deserializer (SerDes) chipset from National Semiconductor Corp. delivers the industry's best output jitter performance of 35 ps peak-to-peak and the best input jitter tolerance of 0.9 units interval (UI) with a bit error rate (BER) of 10 (-15). The SerDes chipset serializes data up to 3.125 Gbps and is well-suited for industrial and medical imaging, communications infrastructure, commercial displays, and test and measurement systems.
The highly integrated chipset includes the DS32ELX0421 serializer and
DS32ELX0124 deserializer. They feature advanced on-chip signal and clock
conditioning circuitry that extends data transmission reach of CAT-6 (shielded
The SerDes' unique architecture replaces the traditional wide single-ended parallel bus with a 5-bit low-voltage differential signaling (LVDS) interface. This breakthrough interface simplifies board layout by reducing the number of input/output (I/O) pins and traces between the serializer, deserializer and field-programmable gate array (FPGA). In addition, the SerDes' LVDS interface reduces electromagnetic interference (EMI), while enabling the use of low-cost FPGAs in a variety of high-speed, high-performance applications.
The SerDes' redundant I/Os and retimed active loop-through enable advanced system configurations such as failover, link aggregation and daisy chaining. Power consumption is less than 1W, and both devices include an automatic standby mode using signal detect and a configurable sleep mode for additional power savings.
"National's new family of high-speed serializers and deserializers is optimized to serve as a front-end chipset to our low-cost Spartan-3 Generation FPGA products," said Oliver Garreau , senior engineering manager in the Spartan FPGA Group at Xilinx. "This SerDes solution supports a broad array of high-speed applications with excellent analog performance, while remaining cost-effective thanks to a high level of integration."