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COSTA MESA, Calif., March 6 /PRNewswire-FirstCall/ -- Irvine Sensors Corporation (Nasdaq: IRSN; Boston Stock Exchange: ISC) announced today that it has successfully demonstrated stacking of four 500 megahertz DDR memorychips without degradation of the chips' operating speed. The Company's demonstration has been verified by the manufacturer of the chips. The Company believes that its demonstration may be an industry-first, since 3-dimensional packaging approaches used by other companies are known to introduce parasitic effects that substantially degrade the speed performance of DDR chips, when stacked. Overcoming this limitation offers new possibilities for packaging of these widely-used memory devices. The Company is actively exploring commercial exploitation of its latest demonstration. Parties interested in discussing such commercialization are urged to contact Keith Gann , Director of 3-D Electronics at email@example.com.
Irvine Sensors achieved its successful demonstration through adaptation of proprietary stacking technologies derived from its long history of developing cognitive vision systems, which require extremely compact and high-speed electronic packaging. Irvine Sensors has an extensive patent portfolio covering these technologies, which has recently been augmented by several new patent awards and notices of awards. The latest additions to the company's 3D electronics patented intellectual property are: Method For Making A Neo-Layer Comprising Embedded Discrete Components (Notice of Allowance received, patent to be issued), Method Of Fabricating Known Good Dies From Packaged Integrated Circuits (U.S. Pat. No. 7,174,627), Process Of Manufacturing A Multilayer Module (U.S. Pat. No. 7,127,807), and Three-Dimensional Imaging Processing Module Incorporating Stacked Layers Containing Microelectronic Circuits(U.S. Pat. No. 7,180,579).
The noticed Neo-Layer(TM) patent covers technologies that enable the assembly of entire systems in a cube. This is a much more challenging objective than the stacking of identical integrated circuit chips, usually memory, into homogeneous packages. Neo-Layers look like identical chips when they go into a stack, but really contain a host of different size chips and passive components allowing all of the electronics in a personal computer, for example, to be stacked in a small number of cubes, as shown below.
The second new Irvine Sensors patent listed above captures the basic approach of creating the Neo-Layers themselves. The approach addresses a fundamental bane of stacked 3D electronics -- the absence of known good die. Nearly all integrated circuit chips are thoroughly tested prior to integration within a system, hence the term "known good". No way has yet been developed to perform comparable testing economically at the die or wafer level. As a result, since conventional chip packaging is inexpensive, industry practice is to test and eliminate non-satisfactory die after packaging. This approach becomes economically less attractive for stacked packages, since a single out-of-specification die can ruin an entire stack. Irvine Sensors' patented Neo-Layer process, on the other hand, involves the modification of an already packaged die that has been tested and shown to be "known-good". The Irvine Sensors process involves the thinning and rewiring of one or more of these known-good die into an embedded layer, now stackable and chip-like in appearance. This new Irvine Sensors patent covers that approach not only for use in stacked packages, but also when the resulting layer is used in a single chip-on-board product that then also benefits from its known good properties.