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Images courtesy SRC Computers

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By David B. Pointer

**SRC Computers**

The polar format algorithm has low computational cost, but it has some limitations that make the backprojection algorithm more attractive. For instance, for backprojection the user can choose any imaging grid, while there is only one imaging grid available for the polar format algorithm. Also, the backprojection algorithm intrinsically allows the ability to add or subtract pulses from an image that is unavailable in any other imaging algorithm.

The backprojection computational technique is broken down into the following steps:

• Image or a slice of a 3-D object is broken down into a set of 1-D projections

• Each projection is filtered individually

• These projections are backprojected together

• Original image or cross-section is reconstructed

The backprojection algorithm is also used extensively in medical imaging. Applications utilizing computed tomography in the medical industry are Single Photon Emission Computerized Tomography (SPECT), Position Emission Tomography (PET), Computed Tomography (CT) Scan or Computed Axial Tomography (CAT) Scan, and Magnetic Resonance Imaging (MRI).

**Conversion Motivation**

The algorithm developers at the Air Force Research Lab (AFRL) use MATLAB for prototyping and long-term evaluation of their computational techniques. The compute time for generating a single 2D image using the entire input data volume takes approximately 1.3 – 1.5 hours based upon the microprocessor performance.

The AFRL group was very interested dramatically reducing this computation time to enhance the productivity of their algorithm developers.

**Microprocessor Implementation **

This implementation converted all of the original MATLAB code into the C Language. The imaging routines implemented on the MAP processor took advantage of many of the optimization techniques supported by the MAP Compiler. These optimizations included spreading the computational array across multiple on-board memory banks, using Block RAM arrays, using two User Logic Chips and overlapping DMAs with compute. The performance of a compute loop when pipelined is one iteration of the loop every clock. The major consumer of computational time was the summation of the contributions of each swath to every voxel in the 2D image. The architecture of the Series H processor provides the ability to structure the algorithm in novel ways.