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In the early days of image processing, the only on-board solutions for actual image processing were ASICs and CPUs. Today, a FPGA can do much of what an ASIC can do, but without the high development costs and the long time-to-market. FPGAs are ideal for image processing, because they feature elements that lend themselves greatly to image processing such as DSP blocks or MAC/ALU blocks. These elements can also be re-configured to perform new tasks that match a specific end-user’s requirements.
Since FPGA chips are essentially “empty” when they are soldered to a PCB, they be can configured to handle image processing functions. This means off-loading image processing functions from the host, thereby accelerating them in many cases.
Matrox Imaging offers a range of products that include a customizable FPGA, as well as a choice of different FPGA chips. At the mid-range level we have the Matrox Solios which features the Altera® Stratix device; at the high-performance end of the spectrum we have the Matrox Odyssey Xpro+, which leverages the Altera® Stratix II device.
Individual processing functions are normally optimized to provide the best possible performance. Performance of a function can be improved simply by processing more pixels in parallel, but this uses more hardware resources and means that fewer functions can be loaded at once. When a required function is not in the FPGA, the data must be transferred to the host for processing so performance will suffer. It’s not always best to code each function for maximum speed, without regard for the resources it uses. Sometimes it’s better to aim for lower-performing functions, which are smaller and use fewer chip resources, thereby allowing a larger range of functions to be loaded simultaneously. Through a user interface, Matrox Imaging will offer a number of FPGA blocks so users can select the ones that make sense for their particular application.
Functions: Host or FPGA
What you can get out of the FPGA depends on what functions you require. Some functions will perform more efficiently on the host, and some will not. Typically, simple point-to-point functions (such as basic image arithmetic) tend to be limited by memory bandwidth. If the host has more bandwidth than the FPGA, then the host will be faster on these functions. More complex functions such as convolutions run slower on the host and are not bandwidth limited. When complex functions are implemented on the FPGA chip, overall performance for the application can be many times better than the host (e.g. as much as 10x better for a convolution with a large symmetric kernel).