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By Dr. Marc Kachelriess, Institute of Medical Physics, University of Erlangen-Nuremberg, Germany; Dr. Michael Knaup, RayConstruct GmbH, Nuremberg, Germany; and Olivier Bockenbach, Mercury Computer Systems, Berlin, Germany
Tomographic image reconstruction is computationally very demanding. In all cases the backprojection represents the performance bottleneck due to the high operational count and the high demand placed on the memory subsystem. In the past, solving this problem has led to the use of Digital Signal Processors and the implementation of specific architectures, connecting Application Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) to the memory through dedicated high-speed busses. More recently, attempts have been made to use Graphic Processing Units (GPUs) and the Cell Broadband Engine processor (CBE).
It is worth noting that, however much these architectures differ, they all share common properties that make them attractive for the implementation of backprojection algorithms: the relative balance of high memory bandwidth and processing capabilities.
The backprojection is a considerable processing step, but a 3D image reconstruction algorithm also includes pre-processing, filtering and post-processing steps. Various devices considered for accelerating the backprojection reveal themselves to be more or less usable for other tasks, requiring more or less assistance from other co-processing units. The implementation of the complete reconstruction pipeline may require the combination of several different devices, influencing the design, implementation and maintenance costs.
Methods and Material Hardware
Four different platforms were selected: