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Updated: October 14th, 2008 10:03 AM CDT

National Semiconductor's New Clock Jitter Cleaners Eliminate Need for VCXO Modules

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via PRNewswire

SANTA CLARA, Calif. , Oct. 14 /PRNewswire-FirstCall/ -- National Semiconductor Corp. (NYSE: NSM) today introduced the industry's first family of clock jitter cleaners capable of providing ultra low-noise clocks without external high-performance voltage-controlled crystal oscillator (VCXO) modules. Using a simple external crystal and cascaded PLLatinum(R) architecture, National's new clock jitter cleaners provide sub-200 femtosecond (fs) root- mean-square (RMS) jitter to improve system performance and accuracy. This level of performance rivals the most expensive VCXO modules.

The new LMK04000 family consists of five precision clock conditioners: LMK04000B, LMK04001B, LMK04011B, LMK04031B and LMK04033B. These devices feature power-to-noise specifications that place them among National's PowerWise(R) family of energy-efficient products. The LMK04000B and LMK04001B offer 24.4 mW-ps per channel, while the LMK04031B and LMK04033B are rated at 25.4 mW-ps per channel and the LMK004011B is 37.4 mW-ps per channel.

The LMK04000 devices provide clean clocks to analog-to-digital converters (ADC), digital-to-analog converters (DAC) and other high-performance components used in wireless infrastructure, test and measurement, and medical ultrasound and imaging equipment. Wireless base station applications include single-carrier and multi-carrier GSM (GSM), Long Term Evolution (LTE), Universal Mobile Telecommunications System (UMTS), Worldwide interoperability for Microwave Access (WiMAX) and Code Division Multiple Access (CDMA) networks.

These clock conditioners are well-matched to work with National's high- speed op amps and ADCs -- such as the LMH6552 fully differential amplifier, LMH6514/15 digital variable gain amplifiers and ADC14V155 high-bandwidth 14- bit ADC -- to provide a complete signal-path system solution.

Key Technical Features - Precision Clock Conditioners

The new LMK04000 family uses National's cascaded PLLatinum architecture, which consists of two high-performance cascaded phase-locked loops (PLL), a low-noise crystal oscillator circuit, a high-performance integrated VCO as well as low-noise dividers and drivers. The first PLL can be configured to use a simple external crystal or a VCXO module to provide the jitter cleaning function while the second PLL uses the integrated VCO to perform low-noise clock generation.

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