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Updated: January 12th, 2011 09:49 AM CDT

Xilinx Introduces the Industry's Highest Performance, Largest Capacity FPGAs for Space Applications

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To meet the unique processing requirements of space-based systems, Xilinx selected four of the highest performance, largest capacity devices across the three Virtex-4 platforms for its new Virtex-4QV family. These devices provide an unprecedented level of system integration among FPGA-based offerings for space applications with up to 200,000 logic cells, 10Mbit of RAM/FIFO, two built-in PowerPC(R) processor blocks with auxiliary processing unit (APU) controller, 512 DSP slices, and four built-in Ethernet MAC blocks.

All Virtex-4QV FPGAs are guaranteed for radiation tolerance, making it possible for aerospace designers to take advantage of high-performance, high-density reprogrammable technology. Extensive testing by Xilinx and the Single Event Effects (SEE) Consortium verifies a total ionizing dose (TID) of 300 krad (Si) and single-event latchup (SEL) immunity greater than 125 MeVcm2/mg with Virtex-4QV devices. The SEE Consortium was founded in 2002 when Xilinx joined forces with NASA's Jet Propulsion Laboratory at the California Institute of Technology, leading the way to the application of SRAM-based reconfigurable FPGA technology in high-radiation environments.

SEAKR's vice president and co-owner Scott Anderson states that, "SEAKR has chosen the Virtex-4QV device for our advanced space processor product line due to its high performance and unprecedented flexibility. The modularity of Xilinx-based processor systems dramatically changes the playing field on what is possible for space applications. The ability to be reprogrammed while in orbit allows our customers to minimize program risks while maximizing their return on investment by being able to entertain new business opportunities with deployed space assets."

Xilinx TMRTool and Single-Event Upset Mitigation Solutions

The Virtex-4QV family is supported with a range of upset mitigation solutions to address environmental circumstances, such as charged particles (e.g., heavy ions or protons), that can alter the state of configuration elements within the FPGA, causing a single event upset (SEU) that produces adverse effects on the expected FPGA functionality. These solutions include triple modular redundancy (TMR) reference designs, extensive application notes that simplify the implementation of advanced configuration memory scrubbing techniques, and the Xilinx TMRTool to automate logic triplication in the FPGA fabric. The TMRTool not only increases productivity with fast, error-free design triplication, but also streamlines the integration of custom-built TMR modules while giving designers control over how the design is triplicated.

Comprehensive Portfolio of Tools and IP

To help accelerate every phase of system design with Virtex-4QV FPGAs, Xilinx offers a comprehensive development ecosystem that includes: ISE(R) FPGA design software; Embedded Development Kit with Platform Studio suite; the XtremeDSP(TM) tools package with System Generator for DSP and AccelDSP(TM) synthesis tool; and the ChipScope(TM) analyzer. It also features a robust library of more than 600 intellectual property (IP) cores, Xilinx training and support services, and application notes that can be downloaded from the Xilinx website.


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