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Updated: July 8th, 2008 05:26 PM CDT

Fujitsu Develops Industry's First CMOS Integrated Circuit That Recovers Clock and Data at 40-44Gbps

via PRNewswire

ISSCC 2007, SAN FRANCISCO , Feb. 13 /PRNewswire/ -- Fujitsu Microelectronics America, Inc. (FMA) today announced that Fujitsu Laboratories of America, Inc. and Fujitsu Laboratories Ltd. have developed the industry's first CMOS IC that performs clock and data recovery (CDR) at 40 to 44Gbps, enabling the future implementation of 40Gbps optical serializer-deserializer modules.

Details on this technology were presented by Fujitsu Laboratories in apaper entitled "A 40-to-44Gb/s 3x Oversampling CMOS CDR/1:16 DEMUX" at the annual International Solid State Circuits Conference (ISSCC), February 13 , in San Francisco .

The paper detailed the first CMOS IC that recovers clock and data at rates of 40 to 44Gbps, and de-multiplexes to 16 x 2.5Gbps. The IC also complies with the ITU G.8251 jitter tolerance mask standard, achieving BER <10(-12) with a2(31)-1 PRBS source. Previous ICs with similar or less functionality have been implemented in SiGe, biCMOS and other compound semiconductor technologies. Those ICs typically dissipated three times as much power as the CMOS version. The low power consumption, along with higher integration and reduced manufacturing cost afforded by CMOS technology, meets the requirements for developing compact form-factor 40Gbps optical SerDes modules.

"This research demonstrates the viability of CMOS for implementing the most difficult circuit blocks in future high-speed optical modules," said William Walker , vice president of the Components and Devices Integration Group at Fujitsu Laboratories of America, Inc. "In the near future, we will be able to demonstrate that the remaining blocks, such as the serializer and limiting amplifier, can also be implemented in CMOS and integrated together with the deserializer on the same IC."

The CMOS CDR, which dissipates 0.91W while operating at 40Gbps, uses anovel 3x oversampling architecture. The die size is 0.8x1.8mm(2) and was fabricated in Fujitsu's 90nm CMOS process. Input data is sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5GHz clock by processing the samples. The ISSCC paper was presented with support from Keio University in Japan , where Keio University students worked with Fujitsu's team.

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