• Home
• Products
• Camera/Sensor
• Data Path
• Display
• Illumination
• Optics
• Processing
• Storage
• AI Magazine
• AI International
• Calendar
• Video Network
• Buyers' Guide
• Careers
• Classifieds
• Advertising Resource Center
• Print: Media Kit
• Online: Overview
• Interactive Rates
• Banner Specifications
• Subscribe

Sign up for our free
Industry eNewsletters

Latest question:
How do you think the new GigE standards will influence the machine vision industry?
Respond or ask your question now!

Telairity Semiconductor (Santa Clara, CA) has released its Telairity-1 multi-core processor architecture that is designed to handle the demanding computational requirements of the H.264 (MPEG-4 part 10) high-definition (HD) codec. The company made the announcement at Hot Chips 17 in Stanford, CA.

H.264 is set to overtake MPEG-2 as the standard by which HD video is compressed in the professional broadcast environment for transmission, storage and editing, where the new standard will deliver the same or better picture quality with a lower bitrate.

The T1P2000 multi-core video processor will be the company's first system-on-chip (SoC) to be built using Telairity-1. Other target applications for the T1P2000 — besides high-definition broadcast television — include videoconferencing, and security and surveillance systems. "We believe these are going to be important applications for us, particularly homeland security and with high-resolution demand picking up," states Shubha Tuljapurkar, Telairity's vice president of marketing and sales.

"We think the high-definition trend is coming in strong, both from a consumer standpoint and from an infrastructure and equipment standpoint as well," Tuljapurkar continues. "What's happening is, because of IPTV and Internet video is becoming very important, all the telcos (telecommunications companies) are getting into the action. We see IPTV becoming very popular; this isn't the case in the U.S. right now, but over time, it will be."

Single-Chip Architecture

Telairity-1 features five independent vector/scalar processors integrated into one chip, along with a video controller and a DRAM controller, which supports 5.3 gigabits per second (GB/s) of I/O bandwidth. "We believe this highest level of integration really carries the smallest footprint, whether it's for security or surveillance," Tuljapurkar says. "This really brings a quantum jump to the market."